Support "include" feature for the Yosys frontend in run vtr flow scripts #2081
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@vaughnbetz - This PR is ready to merge, It would be great to know your thoughts. The CI failures are due to a change in the |
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Signed-off-by: Seyed Alireza Damghani <[email protected]>
- add tests to check the "include" feature works properly for all VTR frontends Signed-off-by: Seyed Alireza Damghani <[email protected]>
build folder to have access to executables for using in VTR scripts (similar to other tools in VTR) Signed-off-by: Seyed Alireza Damghani <[email protected]>
Signed-off-by: Seyed Alireza Damghani <[email protected]>
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…ctory and ignoring them as the design benchmark set for synthesis Signed-off-by: Seyed Alireza Damghani <[email protected]>
Signed-off-by: Seyed Alireza Damghani <[email protected]>
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vaughnbetz
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Jul 14, 2022
vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_odin/config/config.txt
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vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/config.txt
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Description
This PR adds support for passing multiple input designs to the Yosys frontend of the VTR flow using run vtr flow scripts.
CI tests verifying this functionality for all VTR frontends are added correspondingly.
include files, written in supported HDLs by each fronted, are only passed to the frontend for synthesis. The rest will be only copied to the destination folder. This is helpful since users can include memory initialization files in the destination folder.
Related Issue
In accordance with PR #2068
Motivation and Context
Adding benchmarks with multiple design files become available for the Yosys frontend in VTR
How Has This Been Tested?
Types of changes
Checklist: